Department of Informatics Technische Universität München Informatik X: Rechnertechnik und Rechnerorganisation / Parallelrechnerarchitektur Prof. Dr. Arndt Bode , Prof. Dr. Hans Michael Gerndt

Institut für InformatikTU-München Lehr- und Forschungseinheit Informatik X Lehrstuhl für Rechnertechnik und Rechnerorganisation/Parallelrechner Prof. Dr. A. Bode

The FaRM-project investigates in the use of Field Programmable Gate Arrays (FPGAs) as accelerators for microprocessors and rapid prototyping.
 

The Java programming language (and its processor Java Virtual Machine, JVM) from Sun Microsystems Inc. allows system independent execution of programs. In the heterogenous World Wide Web (WWW) it became quickly a pseudo standard, because nearly all computers can now run the same program without modifications. The key to the system independency is also the biggest drawback of Java, its very low execution speed: The host processor has to interprete the JVM code (the bytecode). So Java can be 60 times slower than comparable native programs.

One improvement is the just-in-time compilation (JIT) of the code, here the microprocessor translates the bytecode before execution in native instructions, giving a speedup factor of 5-20. However, it is still significantly slower than native written programs. Unfortunately JIT compiliation is only feasible for well-equipped computers, because the translated code needs 3 to 4 times more memory and the JIT compiler itself is CPU and memory consuming. Additionally, the compilation is also time consuming, so JIT compilation for one-time-used modules is very ineffecient. So the 'pure' JIT-approach is not usable for embedded Java applications ('microcontrollers') and for 'small' network computers (NCs).

A solution for this problem is the development of a silicon-based JVM, a processor that can run the bytecode directly without interpretation. Such chips are already announced or introduced by Sun and Rockwell. Sun's implementation, the picoJava processor, has some optimizations for running the bytecode, like a stack cache and different levels of execution (hardcoded, microcode and emulation).

However, a standard processor is needed anyway in a cheap NC to run the operating system and other non-Java applications. Addionally, the extra cost of a totally new environment (eg. developing new hardware drivers) makes the silicon-based JVM not very attractive.

To make JIT compilation for NCs faster and easier, the possibilities for JIT in FPGAs are being investigated.
There are some requirements that make this task complex if full versatility should be achieved:

• Host CPU independence(eg. x86, Alpha, ARM etc.)
  The JIT-hardware has to be independent from the CPU type, so all CPU specific data has to be in tables and/or can be downloaded without a new hardware synthesis. This affects the possible translation mechanisms and efficiency of translation.
  
  
• Bus connection independence (PCI, USB, simple processor bus etc.)
  The actual translation has to independent from the location of the FPGA in the systems. This leads to a detailed distinction between streaming and random access data. For high latency busses, only streaming mode is usefull. Wherever the various data resides, the translation core has to handle all locations as good as possible, with no (or only minor) changes in the translation process itself. 
  
  
• Extensability of optimization stages
  For a start, only simple (pattern-matching-based) peephole optimization stages are used. Depending on the resource requirements, some of them can be omitted. On the other hand, it should be possible to integrate more complex algorithms easily into the system.
  
  
• Balance between resource needs and speed
  To fit the translation in a wide variety of FPGAs (possibly already used for data acquisition or glue logic in some systems), the JIT concept should allow a trade-off between resource needs (ie. gate count) and compilation and runtime speed.
  
  
  
• Possible use of reconfigurability
  There are also som other tasks in a JVM that can run faster in an FPGA (e.g. class loading and parsing).
  The JIT concept has to take this into account, especially for scheduling the tasks.
  
  
• JVM runtime independence
  The JIT compiler has to be encapsulated, so the integration in various virtual machines needs no changes in the FPGA itself. This affects especially compile-time resolving.

• Dipl. Inform. Georg Acher
• Dr. Carsten Trinitis
• Dipl. Ing. Robert Lindhof

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